(a) Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
(b) Description of the Related Art
Recently, although a flash memory semiconductor has been highly integrated, there is a limit in improvement of the degree of integration due to a physical limit such as an increase of current leakage in a channel according to a conventional 2-dimentional gate structure.
Thus, a novel structure that is able to substitute for the conventional 2-dimentional gate structure, for example, a 3-dimentional vertical NAND (3D VNAND) flash memory that overcomes the limit of the degree of integration by vertically stacking gate structures, has attracted attention. However, since charge distribution is non-uniform in the vertically stacked polysilicon channel layer of the 3D VNAND device, the 3D VNAND device may not be normally operated.
The above information disclosed in this Background section is only to enhance the understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.